reg [DEPTH_LOG:0]stack_point; wire is_full = (stack_point == 2 ** DEPTH_LOG)?1'b1:1'b0; wire is_empty = (stack_point == 'b0)?1'b1:1'b0; always @ (posedge clk ornegedge rst_n) begin//control point of stack if(~rst_n) begin stack_point <= 'b0; endelseif(stack_write_req && stack_read_req) begin//lock stack_point <= stack_point; endelseif(stack_write_req && !is_full) begin//write when stack is not full stack_point <= stack_point + 1'b1; endelseif(stack_read_req && !is_empty) begin// read when stack is not empty stack_point <= stack_point - 1'b1; end end assign stack_full = stack_point[DEPTH_LOG];
always @ (posedge clk ornegedge rst_n) begin//generate empty signal if(~rst_n) begin stack_empty <= 'b0; endelseif(ram_addr == 'b0 && is_empty) begin// delay signal stack_empty <= 1'b1; endelsebegin stack_empty <= 'b0; end end
always @ (posedge clk ornegedge rst_n) begin//generate ram_write_req if(~rst_n) begin ram_write_req <= 'b0; endelseif(!is_full) begin ram_write_req <= stack_write_req; endelsebegin ram_write_req <= 'b0; end end
always @ (posedge clk ornegedge rst_n) begin//prepare the addr and data for push if(~rst_n) begin ram_addr <= 'b0; ram_write_data <= stack_write_data; endelsebegin ram_addr <= stack_point[DEPTH_LOG - 1:0]; ram_write_data <= stack_write_data; end end