reg [DIN_WIDTH_LOG-1:0]shifter_counter; reg [1:0] status,next_status; always @(posedge clk ornegedge rst_n) begin : proc_status if(~rst_n) begin status <= 'b0; endelsebegin status <= next_status; end end
wire is_computed = (shifter_counter == 2 ** DIN_WIDTH_LOG - 1); wire is_traned = dout_valid && !dout_busy; always @(*) begin case (status) INIT:begin if(din_valid) begin next_status = WORK; endelsebegin next_status = INIT; end end WORK:begin if(is_computed) begin next_status = TRAN; endelsebegin next_status = WORK; end end TRAN:begin if(is_traned) begin next_status = INIT; endelsebegin next_status = TRAN; end end default : next_status = INIT; endcase end assign din_busy = status[0];
always @(posedge clk ornegedge rst_n) begin if(~rst_n) begin shifter_counter <= 'b0; endelseif(status == WORK) begin shifter_counter <= shifter_counter + 1'b1; endelsebegin shifter_counter <= 'b0; end end
always @(posedge clk ornegedge rst_n) begin if(~rst_n) begin dout_valid <= 'b0; endelseif(is_computed) begin dout_valid <= 1'b1; endelseif(is_traned) begin dout_valid <= 'b0; end end